The present invention relates in general to a flash memory cell and its memory array and, more particularly, to a scalable dual-bit flash memory cell and its contactless flash memory array for high-density mass storage applications.
A stack-gate flash memory cell is known to be a one-transistor cell, in which the gate length of a cell can be defined by using the minimum-feature-size (F) of technology used. Therefore, the stack-gate flash memory cell is often used in existing high-density flash memory system. Basically, the stack-gate flash memory cells can be interconnected to form different configurations based on the basic logic function, such as NOR, NAND and AND.
The NAND-type flash memory array is formed by interconnecting stack-gate flash memory cells in series with common-source/drain diffusion regions. The density of a NAND-type flash memory array is high, however the read speed is slow for a NAND-type flash memory array due to the series resistance of the configuration. Moreover, a NAND-type flash memory cell is programmed by Fowler-Nordheim tunneling across the thin tunneling-oxide layer between the floating-gate and the common-source/drain diffusion region and its programming speed is relatively slow.
The NOR-type flash memory array is connected with the common-source diffusion lines and each of the common-drain diffusion regions in each column being connected to a bit line through contacts. The read speed of a NOR-type flash memory array is much faster as compared to that of a NAND-type flash memory array. Moreover, a stack-gate flash memory cell in a NOR-type flash memory array is in general programmed by channel hot-electron injection and its programming speed is much faster than that of a NAND-type flash memory array. However, the cell size of a NOR-type flash memory array is about twice as compared to that of a NAND-type flash memory array due to the bit-line contact. Moreover, the programming power is larger and the programming efficiency is low for a NOR-type flash memory array due to the channel hot-electron injection as the programming method.
Another array architecture, which takes advantages of both NOR-type and NAND-type arrays, is shown in FIG. 1, in which FIG. 1A shows a cross-sectional view of a dual-bit flash memory cell and FIG. 1B shows a top plan view of FIG. 1A. As shown in FIG. 1A(a) and FIG. 1B(b), a gate region of a dual-bit flash memory cell including two stack-gate transistors 22G, 20G and a select-gate transistor 24G is formed on a semiconductor substrate 26, in which two common N+/Nxe2x88x92 diffusion regions 22A, 20A are formed in the semiconductor substrate 26 outside of the gate region ; a select-gate line (SG) is formed above two common N+/Nxe2x88x92 diffusion regions and two stack-gate transistors and on a gate dielectric layer 24A being formed on a semiconductor substrate 26. Since the stack-gate transistor, the select-gate transistor and the common N+/Nxe2x88x92 diffusion region can be defined by a masking photoresist step with a minimum-feature-size F, the cell size of each bit in a dual-bit flash memory cell is 4 F2 if the select-gate line and its space can be defined to be a minimum-feature-size F. Apparently, the cell size of FIG. 1 can be made to be comparable to that of a NAND-type flash memory array due to the contactless structure; the read speed of FIG. 1 is much better than that of a NAND-type flash memory array; the programming power and the programming efficiency is much better than that of a NOR-type flash memory array. However, there are several drawbacks that can be easily observed: very high capacitance between the select-gate line (SG) and the common N+/Nxe2x88x92 diffusion regions 22A, 20A; very high capacitance between the select-gate line (SG) and the control-gate lines 22C, 20C; isolation between the common N+/Nxe2x88x92 diffusion regions is poor for the regions outside of the select-gate region 24A; and isolation between nearby select-gate lines is very poor for the regions under the control-gate lines 22C, 20C. It should be emphasized that poor isolation between nearby select-gate lines may result in an erroneous data reading from nearby cells under the same control-gate line.
It is therefore an objective of the present invention to provide a scalable dual-bit flash memory cell having a cell size of each bit being smaller than 2 F2.
It is another objective of the present invention to provide a shallow-trench-isolation structure for scalable dual-bit flash memory cells in nearby rows of an array.
It is further objective of the present invention to provide two common-source and drain conductive bus-lines for a scalable dual-bit flash memory cell with much smaller bus-line resistances and bus-line parasitic capacitances with respect to the semiconductor substrate and the word lines.
It is yet another objective of the present invention to provide a low-voltage select-gate structure for a scalable dual-bit flash memory cell.
Other objectives and advantages of the present invention will be more apparent from the following description.
A scalable dual-bit flash memory cell and its contactless flash memory array are disclosed by the present invention. The scalable dual-bit flash memory cell is formed on a semiconductor substrate of a first conductivity type having an active region formed between two shallow-trench-isolation (STI) regions, wherein the active region has a first conductive layer formed on a first gate-dielectric layer and each of STI regions has a raised field-oxide layer. The scalable dual-bit flash memory cell can be divided into three regions: a first-side region, a gate region, and a second-side region, in which the gate region is located between the first-side region and the second-side region. The first/second-side region comprises a first sidewall dielectric spacer being formed over each sidewall of the gate region and on a portion of a first/second flat bed formed by a common-source/drain diffusion region of a second conductivity type and its nearby etched raised field-oxide layers; a common-source/drain conductive bus line being formed on the first/second flat bed outside of the first sidewall dielectric spacer; and a planarized thick-oxide layer being formed over the common-source/drain conductive bus line and the first sidewall dielectric spacer. The gate region of the first embodiment comprises a pair of second sidewall dielectric spacers being formed over each sidewall of the first sidewall dielectric spacer in the first/second-side region and on the first conductive layer in the active region and the raised field-oxide layers in the STI regions; a pair of floating-gate layers being formed in the active region and being patterned by the pair of second sidewall dielectric spacers; an implant region of the first conductivity type being formed in the semiconductor substrate of the active region between the pair of floating-gate layers; and a planarized control-gate layer over a second gate-dielectric layer being formed over the exposed surfaces of the pair of second sidewall dielectric spacers, the pair of floating-gate layers, the raised field-oxide-layers, and a semiconductor surface of the implanted region. The gate region of the second embodiment comprises a pair of floating-gate layers being patterned by the pair of second sidewall dielectric spacers; an implant region of the first conductivity type being formed in the semiconductor substrate of the active region between the pair of floating-gate layers; and a planarized control-gate layer over a second gate-dielectric layer being formed over the exposed surfaces of the pair of floating-gate layers, the raised field-oxide layers, and a semiconductor surface of the implanted region. A first interconnect-metal layer is formed over the planarized thick-oxide layers or the second gate-dielectric layer in the first/second-side regions and the planarized control-gate layer in the gate region, wherein a hard masking layer including a masking dielectric layer and its two sidewall dielectric spacers is formed over the first interconnect-metal layer to simultaneously pattern and etch the first interconnect-metal layer and the planarized control-gate layer with the masking dielectric layer being aligned above the active region.
A contactless dual-bit flash memory array of the present invention is formed on a semiconductor substrate of a first conductivity type. A plurality of active regions and a plurality of parallel shallow-trench-isolation (STI) regions are formed alternately over the semiconductor substrate, wherein each of the plurality of active regions has a first conductive layer formed over a first gate-dielectric layer and each of the plurality of parallel STI regions has a raised field-oxide layer. A plurality of common bus-line regions and a plurality of gate regions are formed alternately over the semiconductor substrate and transversely to the plurality of parallel STI regions, wherein the plurality of gate regions are formed by a masking photoresist step and are therefore scalable. A plurality of common-source/drain diffusion regions of a second conductivity type are formed in the semiconductor substrate of the plurality of active regions along the plurality of common bus-line regions. A first flat bed being formed in each of the plurality of common-bus line regions is formed alternately by the common-source/drain diffusion region and the etched raised field-oxide layer. A first sidewall dielectric spacer is formed over each sidewall of the plurality of gate regions and on a portion of the first flat bed. A common conductive bus-line is formed over the first flat bed between a pair of the first sidewall dielectric spacers in each of the plurality of common bus-line regions to act as a bit line. A planarized thick-oxide layer is formed over the common conductive bus-line and the pair of the first sidewall dielectric spacers. A plurality of paired floating-gate layers being formed by the first conductive layers in the active regions of each of the plurality of gate regions are patterned by a pair of second sidewall dielectric spacers formed over each inner sidewall of the gate region and on a flat surface being alternately formed by the first conductive layer and the raised field-oxide layer. A plurality of implanted regions being formed in a self-aligned manner in the semiconductor substrate of the active regions between the pair of second sidewall dielectric spacers, wherein each of the plurality of implanted regions comprises a shallow implant region of the first conductivity type for threshold-voltage adjustment and a deep implant region of the first conductivity type for forming a punch-through stop. A plurality of planarized control/select-gate layers together with a plurality of first interconnect-metal layers being formed over a second gate-dielectric layer are simultaneously patterned and etched to form a plurality of word lines transversely to the bit lines by using a set of hard masking layers, wherein each of the hard masking layers being formed on each of the plurality of first interconnect-metal layers comprises a masking dielectric layer being aligned above the active region and two sidewall dielectric spacers being formed over sidewalls of the masking dielectric layer. Similarly, the scalable dual-bit flash memory cell in the contactless dual-bit flash memory array of the present invention may have two floating-gate structures as described.